EE 316 Lab 3 Part 1

Work Problem 8.B, except use excess-2 code instead of excess-3 code. (In excess-2 code, 0 is represented by 0010, 1 by 0011, 2 by 0100, etc.). Any solution with 17 or fewer gates and inverters (not counting the four inverters for the inputs) is acceptable.

-- This file has been automatically generated by SimUAid.

library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

--library SimUAid_synthesis;
--use SimUAid_synthesis.SimuAid_synthesis_pack.all;

entity Lab3part1 is
port(A, B, C, D: in STD_LOGIC;
    S1, S2, S3, S4, S5, S6, S7, AN3, AN2, AN1, 
    AN0: out STD_LOGIC
    );
end Lab3part1;

architecture Structure of Lab3part1 is
	signal 
    Vnet_0, Vnet_1, Vnet_2, Vnet_3, Vnet_4, Vnet_5, Vnet_6, Vnet_7, Vnet_8, Vnet_9, 
    Vnet_10, Vnet_11, Vnet_12, Vnet_13, Vnet_14, Vnet_15, Vnet_16, Ap, Cp, Dp, 
    Vnet_17, Bp, Vnet_18, Vnet_19, Vnet_20, Vnet_21, Vnet_22, Vnet_23, Vnet_24, Vnet_25, 
    Vnet_26, Vnet_27, Vnet_28, Vnet_29: STD_LOGIC;
        component nand2
        port (
                A: in STD_LOGIC;
                B: in STD_LOGIC;
                C: out STD_LOGIC
        );
        end component;
        component nand3
        port (
                A: in STD_LOGIC;
                B: in STD_LOGIC;
                C: in STD_LOGIC;
                D: out STD_LOGIC
        );
        end component;
        component nand4
        port (
                A: in STD_LOGIC;
                B: in STD_LOGIC;
                C: in STD_LOGIC;
                D: in STD_LOGIC;
                E: out STD_LOGIC
        );
        end component;	
        component inverter
        port (
                A: in STD_LOGIC;
                B: out STD_LOGIC
        );
        end component;
begin

VHDL_Device_0: nand2 port map (B, D, Vnet_17);
VHDL_Device_1: inverter port map (A, Ap);
VHDL_Device_2: inverter port map (B, Bp);
VHDL_Device_3: inverter port map (C, Cp);
VHDL_Device_4: inverter port map (D, Dp);
VHDL_Device_5: nand2 port map (Bp, Dp, Vnet_7);
VHDL_Device_6: nand2 port map (Cp, Dp, Vnet_27);
VHDL_Device_7: nand2 port map (A, C, Vnet_29);
VHDL_Device_8: nand2 port map (Ap, Cp, Vnet_16);
VHDL_Device_9: nand2 port map (Bp, D, Vnet_25);
VHDL_Device_10: nand2 port map (C, Dp, Vnet_26);
VHDL_Device_11: nand2 port map (B, C, Vnet_28);
VHDL_Device_12: nand3 port map (Vnet_16, Vnet_25, Vnet_26, Vnet_1);
VHDL_Device_13: nand3 port map (Ap, Cp, Dp, Vnet_0);
VHDL_Device_14: nand3 port map (Vnet_7, Vnet_17, Vnet_16, Vnet_2);
VHDL_Device_15: nand3 port map (Vnet_28, Vnet_29, Vnet_7, Vnet_3);
VHDL_Device_16: nand3 port map (Bp, Vnet_29, Vnet_27, Vnet_4);
VHDL_Device_17: nand4 port map (Ap, C, Vnet_17, Vnet_7, Vnet_5);
VHDL_Device_18: nand2 port map (Vnet_7, Vnet_27, Vnet_6);
VHDL_Device_19: inverter port map (Vnet_5, Vnet_18);
VHDL_Device_20: inverter port map (Vnet_1, Vnet_19);
VHDL_Device_21: inverter port map (Vnet_0, Vnet_20);
VHDL_Device_22: inverter port map (Vnet_2, Vnet_21);
VHDL_Device_23: inverter port map (Vnet_6, Vnet_22);
VHDL_Device_24: inverter port map (Vnet_3, Vnet_23);
VHDL_Device_25: inverter port map (Vnet_4, Vnet_24);
S1 <= Vnet_18;
S2 <= Vnet_19;
S3 <= Vnet_20;
S4 <= Vnet_21;
S5 <= Vnet_22;
S6 <= Vnet_23;
S7 <= Vnet_24;
AN3 <= '1';
AN2 <= '1';
AN1 <= '1';
AN0 <= '0';

end Structure;

Jenny Plunkett

Applications Engineer @ Arm