EE 316 Lab 3 Part 2

a. Write a VHDL module for a tri-state buffer, with 6-bit data inputs and outputs and one control input.
b. Design a 4-to-1 multiplexer with 6-bit data inputs and outputs and two control inputs. Use four tri-state buffers from part (a) and a 2-to-4 decoder.
c. Simulate your code and test it for the following data inputs: 000111, 101010, 111000, 010101

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity decoder2to4 is -- 2 to 4 Line Decoder
        port( 
                A0, A1: in std_logic;
                W, X, Y, Z: out std_logic
        );
end decoder2to4;

architecture bhv1 of decoder2to4 is
begin
        W <= (not A0) and (not A1);
        X <= (not A0) and (A1);
        Y <= (A0) and (not A1);
        Z <= (A0) and (A1);
end bhv1;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity tri_state_buffer is -- Tri-State Buffer
        port(
                input1: in std_logic_vector (5 downto 0);
                enable1: in std_logic;
                output1: out std_logic_vector (5 downto 0)
        );
end tri_state_buffer;

architecture bhv2 of tri_state_buffer is
begin
        output1 <= input1 when (enable1 = '1') else "ZZZZZZ";
end bhv2;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux4to1 is -- 4 to 1 Multiplexer
        port(   
                input0: in std_logic_vector (5 downto 0);
                input1: in std_logic_vector (5 downto 0);
                input2: in std_logic_vector (5 downto 0);
                input3: in std_logic_vector (5 downto 0);
                control1, control2: in std_logic;
                output: out std_logic_vector (5 downto 0)
        );
end mux4to1;


architecture bhv3 of mux4to1 is
component decoder2to4 is -- 2 to 4 Line Decoder
        port( 
                A0, A1: in std_logic;
                W, X, Y, Z: out std_logic
        );
end component;

component tri_state_buffer is
        port(
                input1: in std_logic_vector (5 downto 0);
                enable1: in std_logic;
                output1: out std_logic_vector (5 downto 0)
        );
end component;

signal I0, I1, I2, I3: std_logic;
signal z0, z1, z2, z3: std_logic_vector (5 downto 0);

begin
        decoder: decoder2to4  port map(control1, control2, I0, I1, I2, I3);
        buffer1: tri_state_buffer  port map(input0, I0, z0);
        buffer2: tri_state_buffer  port map(input1, I1, z1);
        buffer3: tri_state_buffer  port map(input2, I2, z2);
        buffer4: tri_state_buffer  port map(input3, I3, z3);
        output <= input0 when (z0/="ZZZZZZ") else
                  input1 when (z1/="ZZZZZZ") else
                  input2 when (z2/="ZZZZZZ") else
                  input3 when (z3/="ZZZZZZ");
end bhv3;

Jenny Plunkett

Applications Engineer @ Arm